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High Speed Low Voltage Logics
This application report (From TI) introduces the various interface standards used today in modern telecom and datacom systems and describes the methods used to interface between similar and different I/O structures used on Texas Instruments serial gigabit solutions products. The main logic levels discussed in this application report are low-voltage positive/pseudo emitter-coupled logic (LVPECL), current-mode logic (CML), voltage-mode logic (VML) and low-voltage differential signaling (LVDS). This document focuses on these four logic levels, because they are now the most prevalent in today’s communications systems. This document deals with the different SERDES devices from Texas Instruments, from input/output structures, various high-speed drivers and receivers, receiver biasing, and termination schemes. Explanations and examples on how to interface different types of drivers and receivers using ac-coupling are also given.
As the demand for high-speed data transmission grows, the interface between high-speed ICs becomes critical in achieving high performance, low power, and good noise immunity. Three commonly used interfaces are PECL (positive-referenced emitter-coupled logic), LVDS (low-voltage differential signals), and CML (current mode logic). When designing high-speed systems, people often encounter the problem of how to connect different ICs with different interfaces. To deal with this, it is important to understand the input and output circuit configurations of each interface for proper biasing and termination. This paper (From Maxim) describes various ways of interconnecting between PECL, CML, and LVDS for high-speed communication systems, using Maxim products as examples.
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